The present invention generally relates to a semiconductor integrated circuit and method of designing the same, and more particularly, to a semiconductor integrated circuit having a polycell structure suited for an emitter coupled logic (ECL) or current mode logic (CML) large scaled integrated circuit (LSI) and to a method of designing such a semiconductor integrated circuit.
Recently, there are demands to produce LSI, using computer aided design (CAD), which operate at a high speed and have a large power consumption, such as ECL, CML and bipolar complementary metal oxide semiconductor (BiCMOS) devices.
For this reason, there is a need to realize a technique for enabling a CAD layout which is both flexible and capable of providing a sufficiently large power supplying capacity.
A unit block and an integrated circuit having a hierarchical structure based on unit blocks were previously proposed in U.S. patent application Ser. No. 492,898 filed Mar. 13, 1990, in which the assignees are the same as the assignees of this application.
The unit block is a hierarchical structure unit in which a plurality of cells having a common height and mutually different widths are arranged in a specific direction taken along the width of the cells. The unit blocks have a standardized width. Each cell forming the unit block has a power consumption which is approximately proportional to the dimension of the cell in the specific direction. For this reason, the unit blocks themselves have a standardized power consumption because the unit blocks have the standardized width. By arranging such unit blocks on a chip, it becomes possible to freely design an arithmetic logic unit (ALU) and the like using bipolar transistors which operate at a high speed.
FIG. 1 shows a typical example of a unit block in a plan view. A unit block 10 includes a plurality of cells 10a respectively having widths Wc, Wc', . . . , and the cells 10a are arranged so that the unit block 10 as a whole has a width L along the X direction. First and second interconnections 10b and 10c, for supplying power, are respectively formed on the top and bottom of the cells 10a, and the unit block 10 as a whole has a height H along the Y direction.
As described above, the unit block 10 has the standardized width L. A plurality of such unit blocks 10 are arranged on a substrate SUB of a semiconductor integrated circuit (chip) as shown in FIG. 2, and macro block 100 which functions as an ALU, for example, is formed on the chip by forming interconnections for connecting the cells 10a of the unit blocks 10 in a predetermined manner. In this case, it is possible to stably supply a sufficient amount of current from a power source to each unit block 10 within the macro block 100 regardless of the arrangement of the unit blocks 10, using a fixed power source system which extends regularly in the Y direction in FIG. 2. Hence, an integrated circuit which is formed using the unit block concept shown in FIG. 2 is particularly suited for a bipolar high-speed operation element such as the ECL, CML and BiCMOS. On the other hand, interconnections among the macro blocks 100 can freely be made using a global channel 101, that is, a gap between the macro blocks 100. Therefore, the integrated circuit having this structure is suited for design by the CAD.
FIG. 3 shows an example of the cell 10a which is used to form the unit block 10. FIG. 3 shows a case where an independent power source voltage V.sub.T is used in addition to power source voltages V.sub.CC and V.sub.EE. An interconnection 10b extends in the X direction at an upper part of the unit block 10 in the Y direction. On the other hand, interconnections 10c1 and 10c2 respectively extend in the X direction at a lower part of the unit block 10 in the Y direction. The interconnections 10b, 10c1 and 10c2 are parallel to each other.
As shown in FIG. 3, a plurality of terminal regions are provided within the cell 10a in correspondence with emitters, collectors and bases of transistors Tr1 through Tr5. However, these terminal regions are provided without considering a specific relationship to the height of the cell 10a, that is, the Y direction. For this reason, when connecting a plurality of cells 10a within the unit block 10 using interconnections, it is necessary to generate a complex interconnection pattern which avoids the terminal regions which should not connect to the interconnections. As a result, there is a problem in that the design of the interconnections using the CAD becomes troublesome and time consuming.
On the other hand, a voltage drop of some sort occurs in the power source voltage within the complex interconnections which are formed on the semiconductor chip for supplying power. However, since the extent of the voltage drop differs depending on the part of the chip, the output levels of transistors which form the integrated circuit differ between the central part and the peripheral part of the chip, for example. As a result, there are problems in that the D.C. margin becomes poor and the propagation delay deviates from the normal value.
Conventionally, the compensation of the voltage drop of the power source voltage is made by making a model of the power source system for the entire chip, and inserting an adjusting resistor at various parts within the chip based on a simulation result of the voltage drop. The resistance of the adjusting resistor is set by controlling the amount of impurities injected into a diffusion region which forms the adjusting resistor based on the estimated voltage drop. However, there is a problem in that such an adjustment is troublesome to carry out. In addition, the calculation of the voltage drop is complex, particularly in the case of a standard cell LSI having a complex power source layout, because a model of such a standard cell LSI is difficult to design using the CAD.